Recent progress in VLSI technology has made integrated circuits with smaller and smaller geometries a reality. As the devices become more miniaturized, however, they become more susceptible to electrostatic discharge (ESD) damages. If not properly contained, ESD can destroy a device, lower reliability and eventually reflect in the bottomline of an electronic device manufacturer.
Protecting a device from the peril of ESD has been quite an endeavor for those skilled in the art. Integrated circuits nowadays are fabricated with many layers of thin film materials such as thermal oxides, dielectric layers, polycrystalline silicon and metal films. The addition of each layer complicates the problem. An example can be found in the forming of metal films using a process where the top layers of both poly-silicon and diffusion regions are deposited and fused with a material such as Ti to form silicides such as TiSi2 for improved sheet conductivity.
This process has been particularly prone to ESD problems. The silicided region of a diffusion comes close to shorting out junctions because of close proximity to the junction. With the improved conductivity, i.e. lower sheet resistance, a contact pad can short with the channel of a MOSFET ("metal-oxide semiconductor field-effect transistor") even if the pad is placed further away than normal. Worse yet, there often exist "silicide asperities" along the diffusion perimeter, where the distance between the silicide and junction varies. When the silicide is too close to the junction, leakage occurs. Further, field implant may cause an N+/substrate junction to avalanche at the top perimeter due to the lower avalanche breakdown voltage at the semiconductor surface than at the junction area below the surface. The avalanche current of this junction may occur right at the point where the silicide is closest to the junction, thus causing leakage or shorts by migrating the silicide into the junction. FIGS. 1 illustrates the cross-sectional view of a typical silicided region with FIG. 2 showing silicide asperities occurring around the perimeter of the N+ region.
To minimize the effect of ESD, protection devices have been constructed for the input and output pads of a device for the purpose of absorbing the sudden surge of ESD. Two commonly used methods of testing a device's ESD tolerance are the Human Body Model (HBM) and the Charged Device Model (CDM). HBM involves simulating the discharge which can occur when an individual touches a device; that is, the human body can be represented by a capacitor of 100 pF charged to a specified voltage and then discharged into the device through a 1500 Ohm resistor. CDM simulates a charged device contacting a metal grounded surface typically associated with automated handling equipment.
Conventional ESD protection structures, which include field snap-back (FSB) transistors, NFET's and N+/substrate diodes, have been found to be ineffective because weak spots are located at random from die to die. Also methods such as increasing NFET channel length, increasing contact-to-channel spacing, adding ESD implant, etc., have been marginal in eliminating rogue pins. Use of a "silicide-block" layer to eliminate problems related to the silicide layer on the I/O sources/drains adds cost to the process.
Therefore, it is desirable to provide ESD protection for devices of small geometries by preventing junctions from avalanching during an ESD discharge. It is also desirable to be able to sink or source the ESD current when it does occur. It is desirable to be able to provide a ballast to minimize damage from avalanching and snap-back and to limit the pad voltage by discharging from pad to Vss. Finally, for fully robust parts, it will be desirable to be able to accommodate the test conditions for both HBM and CDM.